Open AccessImproved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm
Author(s) -
Kulshreshtha Tanmai,
Dhar Anindya Sundar
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5110
Subject(s) - verilog , cordic , very large scale integration , computer science , field programmable gate array , algorithm , application specific integrated circuit , fast fourier transform , computation , matlab , throughput , parallel computing , computational science , computer hardware , embedded system , telecommunications , wireless , operating system
This study presents a very‐large‐scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high‐throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.