Open AccessConstant power consumption design of novel differential logic gate for immunity against differential power analysis
Author(s) -
Saini Harjap,
Gupta Anu
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5093
Subject(s) - power analysis , nand gate , autocorrelation , cmos , computer science , power (physics) , electronic engineering , propagation delay , differential (mechanical device) , logic gate , cadence , mathematics , engineering , algorithm , physics , cryptography , statistics , quantum mechanics , aerospace engineering
Differential power analysis (DPA) method is frequently used for the non‐invasive side‐channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND–NAND, and OR–NOR which can be easily extended for n ‐bit inputs. The design effort is minimal as the structure is such that AND–NAND design can be used to obtain OR–NOR function by just changing the placement of inputs. These gates have 0.46× less propagation delay, and 3.7× higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V.