Open Access14.5 fJ/conversion‐step 9‐bit 100‐kS/s non‐binary weighted dual capacitor array based area and energy efficient SAR ADC in 90 nm CMOS
Author(s) -
Narasimaiah Jagadish Dasarahalli,
Bhat Mujoor Shankaranarayana
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5067
Subject(s) - successive approximation adc , cmos , capacitor , figure of merit , capacitance , voltage , electronic engineering , footprint , electrical engineering , computer science , physics , engineering , optoelectronics , electrode , quantum mechanics , paleontology , biology
In this work, design technique and analysis of low‐energy consumption successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital‐to‐analogue reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routeing. A 9‐bit SAR ADC using the proposed dual CA, implemented in a 90 nm CMOS process, has a small core area footprint of 0.00371 mm 2 . At a 1 V supply and 100 kS/s, the ADC achieves a signal‐to‐noise and distortion ratio of 53.55 dB and consumes 0.47 μW, resulting in a figure‐of‐merit of 14.5 fJ/conversion step.