Open Access2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit
Author(s) -
Gunnam Leenendra Chowdary,
Sung GuoMing,
Weng LeiWen,
Fan TeChia
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.5025
Subject(s) - effective number of bits , oversampling , delta sigma modulation , electronic engineering , electrical engineering , noise (video) , noise shaping , engineering , computer science , cmos , artificial intelligence , image (mathematics)
This study focuses on the design of a 2‐1 switched‐current (SI) multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit. The noise‐cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher‐order quantisation noise from the first stage of the modulator completely. In the proposed differential current‐mode sample‐and‐hold circuit, low‐input impedance is presented with feedback and width‐length adjustment in SI feedback memory cell, a coupled differential replicate with the common‐mode feed‐forward (CMFF) circuit is used to stabilise the common‐mode bias voltage at input terminal, and a differential cross‐connected CMFF circuit is utilised to fix the bias voltages. Post‐layout simulations reveal that the simulated signal‐to‐noise‐and‐distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm 2 .