Open AccessEfficient VLSI architecture for the parallel dictionary LZW data compression algorithm
Author(s) -
Safieh Malek,
Freudenberger Jürgen
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.5017
Subject(s) - computer science , parallel computing , data compression , encoding (memory) , word (group theory) , compression (physics) , compression ratio , algorithm , space (punctuation) , parallel algorithm , theoretical computer science , artificial intelligence , mathematics , materials science , geometry , automotive engineering , engineering , composite material , internal combustion engine , operating system
The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary‐based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries.