Open AccessAn asynchronous mesh NoC based booth multiplication
Author(s) -
He Anping,
Feng Guangbo,
Jilin Zhang,
Wu Jinzhao
Publication year - 2019
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2018.0058
Subject(s) - asynchronous communication , multiplier (economics) , computer science , field programmable gate array , control reconfiguration , virtex , parallel computing , multiplication (music) , asynchronous system , arithmetic , embedded system , computer hardware , clock signal , synchronous circuit , mathematics , computer network , telecommunications , combinatorics , jitter , economics , macroeconomics
The multiplier is one of the most important arithmetic units, which is an essential part of an IC system and affects its efficiency dramatically. The Booth structure of a multiplier is a wide‐used and efficient structure of real IC systems, and the performance of a Booth multiplier would be mainly determined by partial product issues, e.g., multiplication and addition, as well as the frequency of the clock. Then, one of the potential improvements would be the asynchronous control to reduce power by cancelling the global clock, the other be the structure and implementation of the algorithm for high performance, and the last could be the benefits of reconfiguration for sharing process elements. In this paper, we proposed a Booth algorithm which organized by an asynchronous NoC, e.g., the partial product generators are located into a configurable network, and other part of the circuit are organized and adjusted by an asynchronous mechanism. The design is finally implemented by an 8‐bit asynchronous Booth multiplier, which is synthesized and post simulated with a Xilinx Virtex‐7 FPGA development board.