Open AccessEfficient design of coplanar ripple carry adder in QCA
Author(s) -
Sasamal Trailokya Nath,
Singh Ashutosh Kumar,
Ghanekar Umesh
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2018.0020
Subject(s) - adder , quantum dot cellular automaton , computer science , xor gate , cellular automaton , arithmetic , ripple , serial binary adder , carry (investment) , dissipation , efficient energy use , carry save adder , electronic engineering , logic gate , cmos , mathematics , algorithm , electrical engineering , engineering , physics , finance , voltage , economics , thermodynamics
An optimal quantum‐dot cellular automata (QCA) design for full adder (FA) based on an optimal three‐input exclusive‐OR (XOR) gate is presented. This XOR structure utilises a new configuration of cells unlike traditional gate‐level approaches. The coplanar QCA FA spans over 0.03 μ m 2 and delays of 0.5 clock cycles with 40 cells. It achieves total energy dissipation as low as 0.144 eV at 1.5 E k energy level. The utility of proposed gate is leveraged to design a ripple‐carry adder (RCA) as a specific application. For performance evaluation, the authors use traditional cost metrics and QCA‐specific cost function. Results show that proposed n ‐bit RCA outperforms most of the best state‐of‐the‐art designs known in the literature. For example, cell count (area consumption) of 4, 8, and 16 bit adders is 62% (70%), 66% (84%), and 70% (86%) less than the best coplanar RCA design results. In addition, by taking the new cost metrics into account, it is found that proposed adder performs fairly well as compared to the previous adders too. These designs are realised and simulated using QCADesigner.