Open AccessScheme for variable‐frequency digital circuit with data compression based on block‐match process
Author(s) -
Jin Rencheng,
Zhao Jipeng,
Ma Yuan,
Zhou Feng
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2017.0468
Subject(s) - computer science , lossless compression , data compression , data compression ratio , block (permutation group theory) , data transmission , volume (thermodynamics) , computer hardware , electronic engineering , computer engineering , algorithm , image compression , engineering , mathematics , physics , geometry , quantum mechanics , artificial intelligence , image (mathematics) , image processing
In order to find a way to solve the contradiction among storage space, transmission capacity and the data volume in the embedded systems, a data compression scheme based on block matching with an identifier is presented by using the technology of digital integrated circuit. The scheme can achieve lossless real‐time data compression and reduce the volume of the data. Through statistical analysis on the data source, the authors can obtain that such a scheme has many advantages in real‐time performance, a complication of implement, efficiency and practicability. So the digital circuit is considered as a method which can present the encoding process. With the help of QUARTUS II, they combine Verilog and schematic to finish the design hierarchically and code the decompression program by using C language for comparison. The accuracy and efficiency of the circuit are verified with simulation and relevant experiments. The average compression rate is 52.3% with 12 MHz clock frequency and the compression speed on average is 352% faster than the one by using block‐match software algorithm. The scheme would have good performance in many embedded systems.