Open AccessDownscaling AsTeGeSiN threshold switching devices for high‐density 3D memories
Author(s) -
Choi HyunSik
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2017.0459
Subject(s) - materials science , optoelectronics , stacking , annealing (glass) , mobile device , threshold voltage , electrical engineering , computer science , transistor , voltage , physics , nuclear magnetic resonance , composite material , engineering , operating system
In high‐density three‐dimensional (3D) memory technology, a stacking method is used to create memory devices and access devices at the intersections of bit lines and word lines. For this application, access devices should have a high on/off ratio, high current density for writing cycles, and high endurance. Consequently, an arsenic–tellurium–germanium–silicon nitride compound (AsTeGeSiN) threshold switching device with a high current density of 10 4 A/cm 2 above the threshold voltage ( V th ) is reported as a good candidate for use in access devices. In addition, scaling down of access devices as well as memory devices is essential for high‐density 3D memories. However, in AsTeGeSiN threshold switching devices, fast degradation by pulse cycling in smaller devices is observed. To find the main cause of fast degradation by pulse cycling in smaller devices, the low‐frequency noise properties are examined. The rapid increase in the trap density ( N T ) in small devices is the main cause of fast degradation by pulse cycling in AsTeGeSiN devices. On the basis of this evaluation, the author examines the effect of annealing temperature and annealing time on the pulse endurance in smaller devices. Using an annealing temperature of ∼600°C improves the cycling endurance of smaller devices.