Open AccessDesign procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect
Author(s) -
Veldandi Harikrishna,
Rafi Aahmed Shaik
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2017.0419
Subject(s) - shallow trench isolation , transconductance , mosfet , cmos , operational transconductance amplifier , amplifier , channel length modulation , electrical engineering , electronic engineering , engineering , voltage , operational amplifier , trench , materials science , transistor , layer (electronics) , composite material
Nanoscale complementary metal–oxide–semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single‐finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small‐signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current–voltage ( I – V ) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller‐compensated two‐stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post‐layout simulations were performed using standard UMC 65 nm CMOS technology.