Open AccessFault‐tolerant delay cell for ring oscillator application in 65 nm CMOS technology
Author(s) -
Salem Sanaz,
Zandevakili Hamed,
Mahani Ali,
Saneei Mohsen
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2017.0380
Subject(s) - redundancy (engineering) , cmos , topology (electrical circuits) , ring oscillator , fault tolerance , dissipation , computer science , spice , dbc , electronic engineering , engineering , electrical engineering , physics , distributed computing , thermodynamics , operating system
A novel fault tolerant delay cell for ring oscillator (RO) is proposed. As RO is one of the crucial blocks in phased locked loop, delayed locked loo and clock data recovery, it should be tolerated against single event transient (SET) and stuck at faults for harsh environment. Their proposed hybrid fault tolerant topology is combination of triple and quad transistors redundancy, which is applied to the delay cell structure based on the sensitivity role of each transistor. The simulation results with Cadence software show that the proposed fault‐tolerant delay cell dissipates 34.34 µW power, while it occupies 127.2 µm 2 chip area. The proposed topology not only has lower power dissipation in comparison with existing fault tolerant delay cells but also is more reliable against stuck at single and multiple faults and also SETs. By using the proposed reliable delay cell in the RO, the achieved power dissipation and phase noise are about 249 µW and −96 dBc/Hz, respectively, while higher reliability is achieved in comparison with non‐redundant RO s.