Open AccessPLL architecture with a composite PFD and variable loop filter
Author(s) -
K.K. Abdul Majeed,
Kailath Binsu J.
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2017.0336
Subject(s) - phase locked loop , dbc , pll multibit , control theory (sociology) , phase noise , jitter , voltage controlled oscillator , phase frequency detector , delay locked loop , phase margin , materials science , voltage , electronic engineering , engineering , charge pump , computer science , electrical engineering , cmos , operational amplifier , capacitor , amplifier , artificial intelligence , control (management)
A novel phase‐locked loop (PLL) architecture including a composite phase frequency detector (PFD), two charge pumps, variable loop filter topology and voltage‐controlled oscillator is proposed in this study. Composite PFD offers higher‐gain and loop bandwidth (BW) during tracking when Δ ϕ > π and provides a lower‐gain and loop BW during tracking when Δ ϕ < π as well as after lock‐in. The PLL system is designed to ensure stability by maximising and equalising phase margin in both the linear as well as non‐linear operations. The transfer characteristics of composite PFD are free from the blind zone and also found possible to eliminate glitches from the output. A prototype of PLL operating at 2.56 GHz developed on 180 nm complementary metal–oxide–semiconductor process is found to achieve reference spur of −71.4 dBc, lock time of 2.05 μs, peak‐to‐peak jitter of 3.412 ps, phase noise of −110 dBc/Hz at 100 kHz and final placement area of 0.244 m m 2 .