Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

In static random access memory (SRAM), some cells are not selected for writing, but due to the distribution of the word line signals in the SRAM array, their word line signal is activated. Therefore, they may be mistakenly written. Such cells are called half‐selected cells. This study presents two schemes, one for single‐ended and the other for differential sensing SRAMs, to eliminate the half‐selection disturbance. In the first proposed scheme, the content of the desired row of the SRAM array is read before the write operation and is written back on the corresponding write bitlines. This operation results in eliminating the possibility for noise to be written onto the half‐selected cells. In the second scheme, a simple read operation is performed before the write operation. The authors applied their half‐selection resilient schemes to 8 and 6 T SRAMs. Simulation results show that in the presence of radioactive particles, by applying their write‐back scheme to 8 T SRAM and their read‐before‐write scheme to the conventional 6 T SRAM, the failure rate is reduced from an average of 56 and 20%, respectively, to 0. The proposed schemes do not degrade write‐ability of the SRAM cells, and are bit‐addressable. Moreover, their proposed schemes consume smaller amounts of power compared with their rivals.