Open AccessAccurate performance evaluation of VLSI designs with selected CMOS process parameters
Author(s) -
Chang ChiaLing Lynn,
Wen Charles H.P.
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2017.0097
Subject(s) - cmos , leakage (economics) , electronic circuit , benchmark (surveying) , very large scale integration , computer science , process (computing) , electronic engineering , static timing analysis , voltage , engineering , embedded system , electrical engineering , geodesy , economics , macroeconomics , geography , operating system
As process monitors have become vital components in modern very‐large‐scale integration (VSLI) designs, performance targets often determine the physical implementation of such monitors. However, as various process and environmental parameters collectively affect circuit behaviour, the design of process monitors can be difficult. In addition, process parameters from device‐level models may not provide sufficient resolution in circuit‐level performance. Therefore, the authors propose an intelligent novel flow for selecting dominant process parameters for evaluating performance targets such as timing and leakage. The proposed flow is applied to ISCAS'85, ISCAS'89, and IWLS'05 benchmark circuits and selects the dominant parameters in 32 and 45 nm complementary metal‐oxide‐semiconductor (CMOS) technologies. Through this flow, the authors identify the supply voltage, temperature, gate‐oxide thickness, and effective gate length as the four dominant factors for timing and leakage. Experimental results show that the suggested process parameters achieve high evaluation accuracy (<3% errors in timing and <1% errors in leakage on average) in the benchmark circuits. Therefore, the proposed flow can select dominant parameters for performance targets, and the four determined factors can be used to accurately evaluate timing and leakage in 32 and 45 nm CMOS technologies.