Open Access11.39 fJ/conversion‐step 780 kS/s 8 bit switched capacitor‐based area and energy‐efficient successive approximation register ADC in 90 nm complementary metal–oxide–semiconductor
Author(s) -
Dasarahalli Narasimaiah Jagadish,
Tonse Laxminidhi,
Bhat Mujoor Sankaranarayana
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2017.0029
Subject(s) - capacitor , charge sharing , successive approximation adc , integrator , figure of merit , cmos , switched capacitor , electrical engineering , materials science , effective number of bits , voltage , electronic engineering , optoelectronics , physics , engineering
In this study, a design technique for low‐energy consumption and area‐efficient successive approximation register analogue‐to‐digital converter (ADC) is presented. Digital‐to‐analogue conversion equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sample‐and‐hold capacitor, via a switched capacitor integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energy‐efficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm complementary metal–oxide–semiconductor process. The ADC core has a small area footprint of 0.00145 mm 2 and has a figure‐of‐merit of 11.39 fJ/conv‐step.