Open AccessLow‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers
Author(s) -
Sadrafshari Shamin,
Eskandari Razieh,
Hadidi Khayrollah,
Khoei Abdollah
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2016.0445
Subject(s) - jitter , clock generator , cmos , comparator , frequency deviation , phase locked loop , electronic engineering , frequency modulation , clock rate , automatic frequency control , electrical engineering , voltage , physics , engineering , clock signal , radio frequency
This study presents a spread spectrum clock generator (SSCG) circuit for high‐speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage‐controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum‐spreading profile. The control unit consists of an analogue charge pump‐based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high‐speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30–33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm 2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non‐spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.