Open AccessMethod for designing ternary adder cells based on CNFETs
Author(s) -
Tabrizchi Sepehr,
Panahi Atiyeh,
Sharifi Fazel,
Navi Keivan,
Bagherzadeh Nader
Publication year - 2017
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2016.0443
Subject(s) - adder , multiplexer , ternary operation , computer science , carbon nanotube field effect transistor , serial binary adder , transistor , superposition principle , voltage , electronic engineering , sensitivity (control systems) , node (physics) , electronic circuit , field effect transistor , electrical engineering , multiplexing , engineering , cmos , mathematics , telecommunications , programming language , mathematical analysis , structural engineering
Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field‐effect transistors (CNFETs) can easily be utilised for multiple‐ V t circuit designs. In this study, a novel energy‐efficient method for designing one‐digit adder is proposed. The suggested design employ ternary multiplexers to selects u c c e s s o r ¯ andp r e d e c e s s o r ¯ of input trits for the output node values. This study describes the novel ternary multiplexer,s u c c e s s o r ¯ andp r e d e c e s s o r ¯ cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state‐of‐the‐art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.