Open AccessMIPSfpga: using a commercial MIPS soft‐core in computer architecture education
Author(s) -
Harris Sarah L.,
Harris David M.,
Chaver Daniel,
Owen Robert,
Kakakhel Zubair L.,
Sedano Enrique,
Panchul Yuri,
Ableidinger Bruce
Publication year - 2017
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2016.0383
Subject(s) - computer science , debugging , embedded system , field programmable gate array , computer architecture , instruction set , microarchitecture , software , cache , architecture , interface (matter) , set (abstract data type) , operating system , computer hardware , programming language , art , bubble , maximum bubble pressure method , visual arts
In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non‐obfuscated Register‐Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field‐programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands‐on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft‐core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.