Open AccessLow‐jitter DLL applied for two‐segment TDC
Author(s) -
Wu Jin,
Zhang Youzhi,
Zhao Rongqi,
Zhang Kunpeng,
Zheng Lixia,
Sun Weifeng
Publication year - 2018
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2016.0342
Subject(s) - jitter , linearity , phase detector , phase locked loop , differential nonlinearity , detector , offset (computer science) , physics , voltage , materials science , electronic engineering , optics , optoelectronics , computer science , cmos , engineering , quantum mechanics , programming language
A low‐jitter delay‐locked loop (DLL) for high‐resolution time‐to‐digital converter (TDC) is proposed in this study. The generated high accurate and low‐jitter outputs with uniformly distributed multiphase clocks directly from the voltage‐controlled delay line (VCDL) in DLL are applied to two‐segment TDC. For reducing the static phase offset in locked state, the charge pump with interior feedback loop is used to achieve a better current matching between the charging and discharging currents. An improved phase detector as well as a differential VCDL excellent in linearity property and noise suppression is utilised for reducing the output clock jitter. Fabricated by TSMC 0.35 μm complementary metal–oxide–semiconductor process, the measurement results show that DLL's frequency locking range is 60–240 MHz, the output clock jitters at 125 MHz are 3.6 ps for root mean square and 35.07 ps for peak‐to‐peak. By clock period counting and eight‐phase discrimination, the resolution of <1 ns and maximum range of around 1 μs as well as the differential non‐linearity <0.68 LSB and the integration non‐linearity within −0.97 to 1.24 LSB are obtained for two‐segment TDC.