Open AccessVLSI Architecture of Full‐Search Variable‐Block‐Size Motion Estimation for HEVC Video Encoding
Author(s) -
Cheeckottu Vayalil Niras,
Kong Yinan
Publication year - 2017
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2016.0267
Subject(s) - computer science , motion estimation , very large scale integration , block size , coding (social sciences) , ranging , block (permutation group theory) , encoding (memory) , memory bandwidth , pixel , bandwidth (computing) , video processing , frame rate , auxiliary memory , computer hardware , variable (mathematics) , real time computing , computer architecture , computer vision , artificial intelligence , embedded system , key (lock) , mathematics , telecommunications , mathematical analysis , statistics , geometry , computer security
Motion estimation (ME) is the most computationally intensive task in video encoding. This study proposes a full‐search variable‐block‐size ME for the high‐efficiency video coding or H.265 specification. The proposed method reduces memory requirements to a large extent by following a Morton order for data reading and a sum of absolute differences reuse strategy. The data bandwidth demand is also diminished by broadcasting data into multiple processing elements. This ME accelerator supports variable‐block‐size prediction blocks ranging from 8 × 4 to 64 × 64 , and is reconfigurable in various search ranges for a trade‐off between performance and area. The proposed method for very‐large‐scale integration (VLSI) architecture is synthesized with 32 nm technology, and is capable of real‐time encoding of ultra‐high‐definition (4K‐UHD, at 30 Hz) video with a search range of 64 pixels in both horizontal and vertical directions, operating at a frequency of 282 MHz.