Open AccessHigh‐performance VLSI architectures for M‐PSK modems
Author(s) -
Mamidala Chandrakanth,
Dhar Anindya Sundar
Publication year - 2017
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2016.0243
Subject(s) - phase shift keying , very large scale integration , computer science , electronic engineering , demodulation , field programmable gate array , verilog , communications satellite , minimum shift keying , keying , quadrature amplitude modulation , computer architecture , bit error rate , computer hardware , embedded system , engineering , telecommunications , satellite , channel (broadcasting) , aerospace engineering
M‐PSK (phase shift keying) modulation schemes are used in many high‐speed applications like satellite communication, as they are more bandwidth and power efficient compared with other schemes. This study presents very large scale integrated circuits (VLSI) architectures for modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK systems, based on the principle of direct digital synthesis. The proposed modulators do not use any multiplier in contrast to the conventional modulators and hence they are relatively fast and area efficient. Based on the coherent detection technique, this study proposes new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in analogue and digital domains. This study also presents VLSI architectures for all the proposed algorithms. The proposed architectures are described in Verilog and implemented on Xilinx field programmable gate arrays (FPGAs). The simulation results verify their functional validity and implementation results show the suitability of the proposed architectures for satellite communications.