Open AccessResistance‐to‐digital converter designed for high power‐line interference rejection capability
Author(s) -
Gupta Rohit,
George Boby
Publication year - 2017
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2016.0236
Subject(s) - interference (communication) , electronic engineering , linearity , line (geometry) , power (physics) , boost converter , electromagnetic interference , sinadr , ćuk converter , computer science , engineering , electrical engineering , voltage , mathematics , physics , channel (broadcasting) , geometry , quantum mechanics
A novel resistance‐to‐digital converter (RDC), based on the integrating type analogue‐to‐digital converter principle, is presented in this study. The conversion time of the proposed scheme is not a function of the current value of the parameter being measured. Thus, by suitably setting this parameter, the converter can be made to reject the effects of interference at a particular frequency, such as, that due to power‐line at 50/60 Hz. Error analysis was conducted to ascertain the effects of non‐idealities of various components of the circuit, on its output. Simulation studies were carried out in LTSPICE to verify the linearity and the interference rejection capability of the converter. Further, a prototype RDC was developed in the laboratory and tested to confirm the results of the simulation.