Implementation of a decoupling based power analysis attack countermeasure

This study presents new prototyped evaluation results for the authors’ proposed power analysis attack countermeasure architecture based on decoupling individual sensitive modules with low current consumption. The proposed architecture includes a switch box module to randomise internal connections, mixing residual information that may leak through non‐ideal switch elements and uneven charge cycles. The two implementations evaluated are a printed circuit board (PCB) developed using stand‐alone CMOS components and the post‐layout simulation of a circuit developed in 0.18 µm TSMC CMOS technology using Cadence. Both systems were able to protect a decoupled 8‐bit XOR module from a correlation power analysis performed using traces collected at the power supply rail for at least 8000 plaintext inputs. The results show that the countermeasure is suitable for both on‐chip and on‐board designs. Analysis of the measurements collected from the PCB test system demonstrates the need to balance the charge/discharge frequency of the decoupling elements against the operational frequency of the decoupled modules. From the layout, an individual decoupling element was found to be similar in size to the decoupled 8‐bit XOR module, with all four decoupling elements occupying a total of 51% of the layout area. This percentage is expected to decrease in the context of larger, more complex systems.