Open AccessTwo‐parallel pipelined fast Fourier transform processors for real‐valued signals
Author(s) -
Xavier Glittas Antony,
Sellathurai Mathini,
Lakshminarayanan G
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2015.0256
Subject(s) - computer science , parallel computing , fast fourier transform , discrete fourier transform (general) , computation , discrete hartley transform , algorithm , fourier transform , path (computing) , arithmetic , short time fourier transform , mathematics , fourier analysis , mathematical analysis , programming language
This paper presents a set of novel two‐parallel pipelined fast Fourier transform architectures for discrete Fourier transform computation of real‐valued signal. The previous approaches of designing real‐valued fast Fourier transform (RFFT) architectures are the attempts made to make the data path real. Some of the previous designs have partial real data paths (only first two stages are real), whereas the other designs have complete real data‐paths, but reordering registers are required to bring the real and imaginary parts in parallel. Hence, these approaches reduce the number of registers and butterflies only to some extent in the RFFT design. In the proposed designs, feedback‐based scheduling structures are introduced, which reduce the number of registers to half in several stages when compared with the previously known designs. Therefore, the proposed designs require 30% less area and 31.5% less power than the prior designs.