Open AccessDesign and evaluation of a memristor‐based look‐up table for non‐volatile field programmable gate arrays
Author(s) -
Almurib Haider Abbas F.,
Kumar Thulasiraman Nandha,
Lombardi Fabrizio
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2015.0217
Subject(s) - lookup table , field programmable gate array , computer science , memristor , table (database) , gate array , computer hardware , electronic engineering , engineering , data mining , programming language
This study presents the detailed design and analysis of a new memristor‐based look‐up table (LUT) for field programmable gate arrays (FPGAs). The proposed memory utilises memristors as storage elements with N‐type metal–oxide–semiconductor transistors for row access. New WRITE and READ operations are proposed; the proposed LUT requires no additional circuit to handle the WRITE 1 (0) operation. The proposed method requires a RESTORE pulse only for the READ 0 operation. Moreover, the WRITE operation of the proposed method requires three power lines and a RESTORE pulse only for the READ 0 operation, thus saving 25% READ time when compared with previous methods. In addition, the proposed method does not require the REFRESH pulse and does not dissipate power during stand‐by mode. Extensive simulation results are presented with respect to different operational features such as normalised state parameter, pulse width and LUT size. In addition to a circuit‐level evaluation, the proposed LUT scheme has also been assessed with respect to FPGA implementation. Simulation results using sequential benchmarks mapped on Spartan 4 and 5 FPGAs show that the proposed non‐volatile LUT outperforms existing static random access memory cell‐based LUTs in terms of performance.