Open AccessGrouped through silicon vias for lower L d i /d t drop in three‐dimensional integrated circuit
Author(s) -
Mossa Siraj Fulum,
Hasan Syed Rafay,
Elkeelany Omar Sayed Ahmed
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2015.0065
Subject(s) - inductance , power network design , parasitic element , redundancy (engineering) , drop (telecommunication) , through silicon via , interconnection , rlc circuit , capacitance , electronic engineering , materials science , voltage drop , electrical engineering , silicon , computer science , engineering , optoelectronics , capacitor , voltage , physics , reliability engineering , telecommunications , electrode , quantum mechanics
The reliability of three‐dimensional (3D) integrated circuit (IC) is dependent on the yield of through silicon vias (TSVs). Moreover, the highly inductive nature of TSV lead to significant L d i /d t drop especially in the power distribution network, therefore reduction in loop inductance is sought for curtailing L d i /d t drop. In this study, the authors explore the grouping of thinner TSVs to replace a thick TSV (with identical current carrying capability) to reduce the loop inductance of TSVs and provide added redundancy. Closed‐form mathematical equations are derived to calculate resistance inductance capacitance (RLC) parasitic of grouped TSVs. To the best of the authors’ knowledge, this is the first work towards investigating the grouping of thin TSVs to quantitatively analyse the exploits of their lower inductance and inherent redundancy. Their simulation results for power distribution network of 3D IC using conventional TSV and proposed grouped TSV showed that L d i /d t drop improves from minimum of 9% in conventional design to up to 0.08% in the proposed design.