Open AccessInter‐coarse‐grained reconfigurable architecture reconfiguration technique for efficient pipelining of kernel‐stream on coarse‐grained reconfigurable architecture‐based multi‐core architecture
Author(s) -
Kim Yoonjin,
Joo Hyejin,
Yoon Sohyun
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2015.0047
Subject(s) - control reconfiguration , computer science , kernel (algebra) , parallel computing , bottleneck , computer architecture , architecture , flexibility (engineering) , multi core processor , exploit , distributed computing , embedded system , mathematics , art , statistics , computer security , combinatorics , visual arts
Coarse‐grained reconfigurable architecture (CGRA)‐based multi‐core architecture aims at achieving high performance by kernel‐level parallelism (KLP). However, the existing CGRA‐based multi‐core architectures suffer from high energy consumption and performance bottleneck when trying to exploit the KLP because of poor resource utilisation caused by insufficient flexibility. In this study, the authors propose a new ring‐based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilisation focusing on the kernel‐stream type of the KLP. In addition, they introduce a novel inter‐CGRA reconfiguration technique for the efficient pipelining of kernel‐stream based on the RSF. Experimental results show that the proposed approaches improve performance by up to 88.8% and reduce energy by up to 48.2% when compared with the conventional CGRA‐based multi‐core architectures.