Open AccessCompensation method of the excess loop delay in continuous‐time delta‐sigma analog‐to‐digital converters based on model matching approach
Author(s) -
Guo Jia,
Magaña Mario E.
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2014.0368
Subject(s) - compensation (psychology) , control theory (sociology) , loop (graph theory) , delta sigma modulation , matching (statistics) , converters , sigma , delay locked loop , filter (signal processing) , mathematics , feedback loop , computer science , statistics , physics , phase locked loop , power (physics) , telecommunications , jitter , psychology , control (management) , bandwidth (computing) , computer security , combinatorics , quantum mechanics , artificial intelligence , psychoanalysis , computer vision
Continuous‐time (CT) delta‐sigma (Δ∑) analog‐to‐digital converters (ADCs) have one important constrain, namely the excess loop delay. Most excess loop delay compensation methods need to know the exact value of the excess loop delay in advance. However, the value of the excess loop delay is a uniformly distributed random variable. To improve system performance with the same loop filter, a new compensation algorithm for the excess loop delay of CT Δ∑ ADCs based on the model matching method is presented in this study. Compared with previous compensation methods, the model matching algorithm is more practical because the value of the excess loop delay varies randomly every clock period. It is shown through simulation that a mean value based algorithm can improve the SQNR performance of CT Δ∑ ADCs for the most probable values of the excess loop delay.