Open AccessMulti‐standard high‐throughput and low‐power quasi‐cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards
Author(s) -
Kanchetla Vijaya Kumar,
Shrestha Rahul,
Paily Roy
Publication year - 2016
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2014.0347
Subject(s) - low density parity check code , computer science , interoperability , throughput , decoding methods , wireless , subcarrier , clock rate , orthogonal frequency division multiplexing , computer hardware , electronic engineering , embedded system , chip , computer network , algorithm , telecommunications , engineering , channel (broadcasting) , operating system
This study presents a reconfigurable quasi‐cyclic low density parity check (QC‐LDPC) decoder for IEEE 802.16e worldwide interoperability for microwave access and IEEE 802.11n wireless fidelity communication standards. It supports multiple code‐rates of 1/2, 2/3, 3/4, 5/6 and its architecture has been designed based on column layered decoding technique to enhance the convergence speed. The authors have suggested a register file based approach to handle the shift property of the modified parity check matrix and a modified version of the matrix permutation method has been introduced to reduce the number of check nodes which handle multiple messages. In addition, parallel processing has been incorporated in the decoder architecture to attain higher achievable throughput. This QC‐LDPC decoder is implemented in 90 nm CMOS process and is post‐layout simulated. It can achieve a throughput of 796 Mbps for a code‐rate of 5/6. With 0.9 V supply, it consumes 146 mW of total power at 149 MHz clock frequency.