Open AccessDecoder architecture for generalised concatenated codes
Author(s) -
Spinner Jens,
Freudenberger Jürgen
Publication year - 2015
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2014.0278
Subject(s) - bch code , computer science , concatenated error correction code , soft decision decoder , decoding methods , block code , serial concatenated convolutional codes , algorithm , parallel computing , error detection and correction , reed–solomon error correction , arithmetic , mathematics
This paper proposes a pipelined decoder architecture for generalised concatenated (GC) codes. These codes are constructed from inner binary Bose–Chaudhuri–Hocquenghem (BCH) and outer Reed–Solomon codes. The decoding of the component codes is based on hard decision syndrome decoding algorithms. The concatenated code consists of several small BCH codes. This enables a hardware architecture where the decoding of the component codes is pipelined. A hardware implementation of a GC decoder is presented and the cell area, cycle counts as well as the timing constraints are investigated. The results are compared to a decoder for long BCH codes with similar error correction performance. In comparison, the pipelined GC decoder achieves a higher throughput and has lower area consumption.