Open AccessLow‐power secure S‐box circuit using charge‐sharing symmetric adiabatic logic for advanced encryption standard hardware design
Author(s) -
Monteiro Câncio,
Takahashi Yasuhiro,
Sekine Toshikazu
Publication year - 2015
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2014.0150
Subject(s) - charge sharing , computer science , electrical engineering , power analysis , glitch , adiabatic process , electronic engineering , computer hardware , cmos , physics , voltage , engineering , cryptography , computer security , thermodynamics
The previously proposed charge‐sharing symmetric adiabatic logic (CSSAL) in an 8‐bit S‐box circuit is implemented in this paper using a multi‐stage positive polarity Reed–Muller representation with a composite field technique. The CSSAL and other conventional dual‐rail adiabatic logics are evaluated from the view point of the transitional power fluctuation and the peak current traces in the 8‐bit S‐box in order to compare their resistance against side‐channel attacks. A method to eliminate unwanted glitch current, the triple power clock supplies are applied to each inversion block; thus, the CSSAL S‐box circuit performs uniform peak current traces and it has significant power reduction, which is applicable for high security demand and low power devices, such as smart cards, radio frequency identity tags or wireless sensors. The results are obtained from the SPICE simulation with a 0.18‐μm 1.8‐V standard complementary metal–oxide semiconductor technology at an operating frequency band of 1.25 KHz–70 MHz.