Open AccessFault tolerant architecture design using quad‐gate‐transistor redundancy
Author(s) -
Mukherjee Atin,
Dhar Anindya Sundar
Publication year - 2015
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2014.0106
Subject(s) - redundancy (engineering) , triple modular redundancy , transistor , modular design , computer science , electronic engineering , fault tolerance , benchmark (surveying) , electronic circuit , embedded system , reliability engineering , engineering , electrical engineering , distributed computing , geography , operating system , geodesy , voltage
In the current era of speed and recent trend of device miniaturisation, failure rates have been increased with the increase in the design complexity and the density of transistors in chip and hence reliability issues at circuit level have become more prominent and challenging. In this study, the authors propose a new static fault tolerant method called quad‐gate‐transistor, which uses quadded‐transistor output logic with gate level quad implementation of the given circuitry to make the system defect tolerant. Such combination of gate and transistor level redundancy provides significantly higher reliability over classical triple modular redundancy and other existing static approaches as supported by extensive simulation results using some of the ISCAS 85 benchmark and other standard circuits. The proposed method also takes care of most of the limitations that restrict the use of the existing static methods in practical applications.