Low power sub‐threshold asynchronous quasi‐delay‐insensitive 32‐bit arithmetic and logic unit based on autonomous signal‐validity half‐buffer

The authors propose an asynchronous‐logic (async) quasi‐delay‐insensitive (QDI) autonomous signal‐validity half‐buffer (ASVHB) realisation approach for low power sub‐threshold operation ( V DD = 0.2 V). There are three key attributes in the proposed ASVHB realisation approach. First, the ASVHB realisation approach embodies integrated autonomous validity signals, which are unique and are used exclusively to simplify the circuit implementation for QDI protocol. Second, the ASVHB realisation approach applies the fine‐grained gate‐level method, which propagates data through a single‐cell datapath pipeline to maximise the throughput rate. Third, the ASVHB realisation approach adopts the static‐logic implementation, which maintain stable output states (by connecting them directly to the power rails), to feature high robustness for sub‐threshold operation. They compare their ASVHB realisation approach against the competitive reported weak‐conditioned half‐buffer (WCHB) and pre‐charged half‐buffer (PCHB) realisation approaches. The WCHB and PCHB library cells, on average, require ∼2.1 × and ∼1.9 × more transistors than the ASVHB library cells. With respect to a 3‐stage pipeline realisation, the WCHB and PCHB pipelines, on average, require 1.8 × and 1.5× more transitions per‐cycle than the ASVHB pipeline. They design an async 32‐bit arithmetic and logic unit (ALU) based on the proposed ASVHB realisation approach (at 65 nm CMOS process). Their ASVHB ALU occupies 0.092 mm 2 , and in many merits, outperforms the WCHB and PCHB counterparts. The WCHB and PCHB counterparts require ∼1.7 × and ∼1.4× more transistors, respectively, than their design. At the sub‐threshold voltage of V DD = 0.2 V, the WCHB and PCHB counterparts dissipate ∼1.7× and ∼2.6× more energy, respectively, and are, respectively, ∼0.95× and ∼0.73× slower throughput.