Open AccessSleep power minimisation using adaptive duty‐cycling of DC–DC converters in state‐retentive systems
Author(s) -
Balsamo Domenico,
Brunelli Davide,
Paci Giacomo,
Benini Luca
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0466
Subject(s) - capacitor , converters , duty cycle , computer science , boost converter , power management , voltage , electrical engineering , software , power (physics) , electronic engineering , engineering , physics , quantum mechanics , programming language
Aggressive power management techniques, which combine hardware and software solutions, are fundamental for embedded computing platforms today, especially if they are battery operated. This paper proposes an adaptive low‐level algorithm, which modulates the DC–DC converter activation for minimising quiescent current consumption. This algorithm allows a discontinuous usage of the DC–DC converter during the sleep time, without requiring modification in the user's main program, by powering the system solely with the internal DC–DC converter capacitor and without using any other additional capacitors as an energy buffer. The algorithm computes the maximum interval between consecutive wake‐ups necessary for the capacitor recharging at run‐time. Intervals are decided by taking into account both the global leakage and the temperature‐dependent variations of the capacitor. The proposed solution significantly enhances the lifetime of applications with a low activity rate, such as wireless sensor networks, while still guaranteeing efficient power delivery for high‐current demand intervals.