Open AccessParallel very large‐scale integration chip implementation of optimal fractional motion estimation
Author(s) -
Hsia ShihChang,
Chen LungSen
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0465
Subject(s) - motion estimation , very large scale integration , computer science , quarter pixel motion , chip , gate count , cmos , pixel , interpolation (computer graphics) , frame rate , computer hardware , parallel computing , computer engineering , real time computing , algorithm , electronic engineering , embedded system , artificial intelligence , engineering , motion (physics) , telecommunications
Fractional motion estimation (ME) is commonly employed to improve motion compensation in video coding. However, the computational complexity is generally too high for real‐time applications. This study proposes an efficient quarter‐pixel estimation method implemented at both the algorithm and architecture levels. This approach to rapid estimation adopts a local full‐search method to reduce the computational requirements while maintaining coding quality. We also developed a fast sub‐pixel interpolation and parallel very large‐scale integration (VLSI) architecture for quarter estimation to enhance processing speed. The overall VLSI architecture was developed for the estimation of fractional motion using a cell‐based design. Three engines were implemented within a parallel structure: integer ME, sub‐pixel interpolation and factional ME. The inclusion of pipeline scheduling enables the processing of one macro‐block within 240 cycles. The gate count was ∼316 k and the maximum frequency was ∼160 MHz when implemented using Taiwan Semiconductor Manufacture Company 0.18 µm complementary metal oxide semiconductor process. The proposed chip achieved a throughput‐rate of 662 k blocks per second.