Open AccessA 2.67 fJ/c.‐s. 27.8 kS/s 0.35 V 10‐bit successive approximation register analogue‐to‐digital converter in 65 nm complementary metal oxide semiconductor
Author(s) -
Zhu Zhangming,
Qiu Zheng,
Shen Yi,
Yang Yintang
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0446
Subject(s) - comparator , successive approximation adc , figure of merit , linearity , dynamic range , capacitor , analog to digital converter , voltage , effective number of bits , electrical engineering , electronic engineering , leakage (economics) , materials science , cmos , physics , computer science , optoelectronics , engineering , economics , macroeconomics
A design of a 10‐bit 27.8 kS/s 0.35 V ultra‐low power successive approximation register (SAR) analogue‐to‐digital converter (ADC) is presented. Nano‐watt range power consumption is achieved thanks to the proposed segmented‐capacitor array structure and ultra‐low voltage design. To facilitate ultra‐low voltage operation, a bulk‐driven based fully dynamic comparator is proposed. A novel latched dynamic logic cell is introduced to eliminate decision error caused by leakage current. Boosting technique is introduced in digital‐to‐analogue converter (DAC) driving switch to relieve non‐linearity. A new double‐boosted sample switch is employed to reduce leakage current and improve sampling linearity. The ADC was fabricated in 65 nm complementary metal oxide semiconductor. Drawing 25.2 nW from a single 350 mV supply, the ADC achieves 52.14 dB signal‐to‐noise distortion ratio and 8.4‐bit effective number of bits resulting in a figure‐of‐merit of 2.67 fJ/conversion‐step.