Guest Editorial

Mobile computing systems, multimedia content players and medical electronics are some of the applications that are driving strong growth in VLSI technology. Although the nanoscale CMOS Field Effect Transistor (FET) is going strong with room for further scaling, other nanoelectronics technologies like Multigate FET, Graphene FET, Tunnel FET, are being researched widely as possible successors. Though the key issues in design such as managing power consumption, leakage, thermal effects, process variation, reliability and security remain the same, newer technologies provide additional levers to address those problems. However, integrating new solutions with current methodologies, whereas producing robust and efficient chips with both high-design productivity and manufacturing yield remains a challenge. With this context in mind, the Special Issue on ‘Design Methodologies for Nanoelectronic Digital and Analog Circuits’ has been brought to serve VLSI researchers and design engineers. Authors were invited to publish their original work in topics ranging from design methodologies for emerging and exploratory technologies to methodologies for system level design. Though this Special Issue was designed to attract papers from the authors of the 2012 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2012), the submissions were open to all authors. This Special Issue collects contributions that are substantially revised versions of the papers that appeared in the conference proceedings of the ISVLSI 2012. The goal of the ISVLSI conference was to bring together researchers and practitioners working on theory, techniques and applications of VLSI design systems involving circuits, design, synthesis, analysis and system applications of VLSI design principles. Based on reviewer recommendations, eight leading research papers were accepted for publication in this Special Issue. Consistent with accepted practice, the journal versions of the conference papers were substantially extended and revised further following the peer-review assessment. The range of the papers published in this Special Issue address diverse areas from the design applications of emerging technologies, to practical issues faced by current design engineers. The research issues of physical design optimisation, circuit-level design exploration for nanoelectronic technology, and system level methodologies for task scheduling on multi-core systems, are covered by this set of papers. The guest editors are extremely thankful to the reviewers for their timely reviews. A majority of the reviewers were chosen from the program committee of the ISVLSI 2012 conference, representing experts in their fields who provided high quality reviews for the papers. We thank the authors for their patience, diligence and dedication at all stages of the review process. We are grateful to the ISVLSI 2012 conference organisers and Dr. Asim Ray, Editor-in-Chief, IET Circuits, Devices & Systems, for making this Special Issue possible.