Open AccessSpur reducing architecture of frequency synthesiser using switched capacitors
Author(s) -
Mandal Debashis,
Mandal Pradip,
Bhattacharyya Tarun Kanti
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0200
Subject(s) - switched capacitor , architecture , capacitor , spur , electrical engineering , engineering , geography , voltage , structural engineering , archaeology
This study presents a new spur reducing architecture of phase‐locked loop‐based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi‐spaced time intervals. It reduces fundamental as well as higher‐order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture.