Open AccessDevelopment of low‐complexity all‐digital frequency locked loop as 500 MHz reference clock generator for field‐programmable gate array
Author(s) -
Yuwono Sigit,
Han SeokKyun,
Yoon Giwan,
Cho HanJin,
Lee SangGug
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0175
Subject(s) - clock generator , gate array , phase locked loop , loop (graph theory) , electrical engineering , generator (circuit theory) , electronic engineering , computer science , clock rate , signal generator , physics , clock signal , field programmable gate array , computer hardware , engineering , mathematics , power (physics) , electronic circuit , phase noise , voltage , chip , combinatorics , quantum mechanics
The authors report the development of an on‐chip 500 MHz reference clock generator as a part of a clock manager for a field‐programmable gate array. The generator is implemented in the form of an all‐digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under‐sampled 1‐bit ΔΣ frequency‐to‐digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase‐and‐frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.