Open AccessDesign techniques for decision feedback equalisation of multi‐giga‐bit‐per‐second serial data links: a state‐of‐the‐art review
Author(s) -
Yuan Fei,
ALTaee Alaa R.,
Ye Andy,
Sadr Saman
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2013.0159
Subject(s) - computer science , electronic engineering , channel (broadcasting) , implementation , bandwidth (computing) , data transmission , serial communication , intersymbol interference , transmission (telecommunications) , power consumption , state (computer science) , reflection (computer programming) , bit error rate , computer engineering , power (physics) , engineering , computer hardware , telecommunications , algorithm , physics , quantum mechanics , programming language
This study provides a comprehensive review of decision feedback equalisation (DFE) for multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps serial links reported in the past decade are compiled and presented. The imperfection of wire channels, in particular, finite bandwidth, reflection and cross‐talk and their impact on data transmission are investigated. The fundamentals of both near‐end and far‐end channel equalisation to combat the effect of the imperfection of wire channels at high frequencies are explored. A detailed examination of the principle, configuration, operation and limitation of DFE is followed. Design challenges encountered in design of DFE for multi‐Gbps data links including timing constraints, sampling, error propagation, arithmetic operation, highly dispersive channels, power consumption and techniques and circuit implementations that address these challenges are studied. The need for adaptive DFE and the principles of adaptive DFE are investigated. Finally, the performance of various adaptive DFEs is examined and their pros and cons are compared.