Open AccessVLSI implementation of high‐throughput parallel H.264/AVC baseline intra‐predictor
Author(s) -
Hsia ShihChang,
Chou YingChao
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2013.0097
Subject(s) - chrominance , computer science , encoder , parallel computing , coding (social sciences) , very large scale integration , computation , computer hardware , algorithm , block (permutation group theory) , luminance , real time computing , embedded system , artificial intelligence , mathematics , statistics , geometry , operating system
This study presents a parallel very large scale integrated circuits architecture for an intra‐predictor based on a fast 4 × 4 algorithm. For real‐time scheduling, the proposed algorithm overcomes the data dependency between intra‐prediction and intra‐coding, thereby improving coding performance and reducing the number of coding cycles. The high‐speed architecture for intra‐prediction includes configurable computation cores to process YUV components using 10 pixel parallelism. Prediction for one macro‐block (MB) coding (luminance: 4 × 4 and 16 × 16 block modes; chrominance: 8 × 8 block modes) can all be completed within 256 cycles. The proposed architecture achieves throughput of 410 kMB/s, suitable for 1920 × 1080/35 Hz 4:2:0 HDTV encoder at a working frequency of 105 MHz.