Open AccessTiming variation aware dynamic digital phase detector for low‐latency clock domain crossing
Author(s) -
Lodhi Faiq Khalid,
Hasan Syed Rafay,
Sharif Naeha,
Ramzan Nadra,
Hasan Osman
Publication year - 2014
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2013.0067
Subject(s) - metastability , asynchronous communication , microelectronics , detector , computer science , phase detector , latency (audio) , electronic engineering , clock skew , phase (matter) , digital electronics , real time computing , low latency (capital markets) , algorithm , electrical engineering , electronic circuit , engineering , jitter , telecommunications , clock signal , physics , quantum mechanics , voltage , computer network
This study presents a digital phase detector‐based approach for estimating and synchronising phase variations between clock domains. Instead of waiting for the resolution of metastability (with finite probability of failure), the authors propose a metastability avoidance algorithm, based on a sampling method for asynchronous signals. The results, using 90 nm inovation for high performance microelectronics (IHP) technology, show that the proposed design is about 1.5 times faster and provides a 35% improvement in Energy‐Delay Product compared with the state‐of‐the‐art approaches. Moreover, it completely prevents metastability failures.