Open Access1–5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector
Author(s) -
Byun Sangjin,
Son Chung Hwan,
Hwang Jongil,
Min ByungHun,
Park MunYang,
Yu HyunKyu
Publication year - 2013
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2013.0023
Subject(s) - offset (computer science) , cmos , detector , phase detector , phase (matter) , materials science , optoelectronics , electronic engineering , electrical engineering , physics , computer science , optics , engineering , voltage , quantum mechanics , programming language
This study presents a 1–5.6 Gb/s CMOS clock and data recovery (CDR) integrated circuit (IC) implemented in a 0.13 μm CMOS process. The CDR uses a half‐rate linear phase detector (PD) of which static phase offset is compensated by an additional binary PD and a digital charge pump (CP) calibration block. During initialisation, the static phase offset is detected by the binary PD and the CP current is controlled accordingly to compensate the static phase offset. Also, the architecture of this CDR IC is designed for a clock embedded serial data interface which transfers CDR training clock patterns before normal random data signals. The implemented IC consumes 16–22 mA from a 1.2 V core supply for data rates of 1–5.6 Gb/s and 20 mA from a 3.3 V I/O supply for two preamplifiers and low‐voltage differential signalling drivers. When the 2 31 –1 pseudorandom binary sequence is used, the measured bit‐error rate is better than 10 –12 and the jitter tolerance is 0.3UI pp . The recovered clock jitter is 21.6 and 4.2 ps rms for 1 and 5.6 Gb/s data rates, respectively.