Open AccessDigital calibration technique using a signed counter for charge pump mismatch in phase‐locked loops
Author(s) -
Jeong ChanHui,
Kim KyuYoung,
Kwon ChanKeun,
Kim Hoonki,
Kim SooWon
Publication year - 2013
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2013.0011
Subject(s) - calibration , cmos , charge pump , power (physics) , phase (matter) , phase locked loop , electronic engineering , materials science , physics , computer science , voltage , electrical engineering , engineering , capacitor , quantum mechanics
The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase‐locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .