Open AccessEvaluation and mitigation of performance degradation under random telegraph noise for digital circuits
Author(s) -
Chen Xiaoming,
Luo Hong,
Wang Yu,
Cao Yu,
Xie Yuan,
Ma Yuchun,
Yang Huazhong
Publication year - 2013
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2012.0361
Subject(s) - degradation (telecommunications) , digital electronics , reliability (semiconductor) , electronic circuit , electronic engineering , noise (video) , computer science , node (physics) , sizing , circuit reliability , power (physics) , electrical engineering , engineering , artificial intelligence , physics , art , visual arts , structural engineering , quantum mechanics , image (mathematics)
Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution‐based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.