Open AccessGeostatistical‐inspired fast layout optimisation of a nano‐CMOS thermal sensor
Author(s) -
Okobiah Oghenekarho,
Mohanty Saraju P.,
Kougianos Elias
Publication year - 2013
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
eISSN - 1751-8598
pISSN - 1751-858X
DOI - 10.1049/iet-cds.2012.0358
Subject(s) - metamodeling , cmos , design space exploration , kriging , computer science , electronic circuit , electronic engineering , integrated circuit , netlist , design of experiments , integrated circuit design , computer engineering , engineering , embedded system , machine learning , mathematics , electrical engineering , programming language , statistics , operating system
Continuous and aggressive scaling of semiconductor technology has led to persistent and dominant nanoscale effects on analogue/mixed‐signal (AMS) circuits. Design space exploration and optimisation costs using conventional techniques have increased to infeasible levels. Hence, growing research for alternative design and metamodelling techniques with a much reduced design space exploration and optimisation cost and high level of accuracy, continues to be very active. This study presents a geostatistical inspired metamodelling and optimisation technique for fast and accurate design optimisation of nano‐complementary metal oxide semiconductor (CMOS) circuits. The design methodology proposed integrates a simple Kriging technique with efficient and accurate prediction characteristics as the metamodel generation technique. A gravitational search algorithm (GSA) is applied on the generated metamodel (substituted for the circuit netlist) to solve the design optimisation problem. The proposed methodology is applicable to AMS circuits and systems. Its effectiveness is illustrated with the optimisation of a 45 nm CMOS thermal sensor. With six design parameters, the design optimisation time for the thermal sensor is decreased by 90% and produces an improvement of 36.8% in power consumption. To the best of the authors' knowledge this is the first work to use GSA for analogue design optimisation.