Open AccessLow‐power 6‐GHz wave‐pipelined 8 b × 8 b multiplier
Author(s) -
Saha Aloke,
Pal Dipankar,
Chandra Mahesh
Publication year - 2013
Publication title -
iet circuits, devices and systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.251
H-Index - 49
ISSN - 1751-8598
DOI - 10.1049/iet-cds.2012.0221
Subject(s) - multiplier (economics) , flip flop , interconnection , clock rate , transistor , dissipation , computer science , propagation delay , electronic engineering , cmos , parallel computing , electrical engineering , physics , engineering , telecommunications , voltage , economics , macroeconomics , thermodynamics
In this study, a low‐power, high‐speed, layout‐efficient 8 b × 8 b unsigned parallel multiplier based on pair‐wise algorithm with wave‐pipelining is introduced. Simplified interconnection and data propagation in forward direction with no feedback in pair‐wise multiplication technique is the key to achieve high‐performance wave‐pipelined multiplier. In the proposed work, normal process complementary pass‐transistor logic is used to build all the leaf cells of combinational block. The input/output registers are designed with high‐performance pulse‐triggered true single‐phase clocking flip flop. Post‐layout simulation with Taiwan Semiconductor Manufacturing Company Limited 0.18 µm single‐poly double‐metal complimentary metal oxide semiconductor technology using Tanner EDA V.13 shows that the proposed multiplier works at 6.25 GHz clock frequency and achieves the throughput of 6.25 billion multiplications per second with average power dissipation of 18.54 mW and overall latency of 3.24 ns at 25°C temperature and at 2 V supply rail.