Open AccessEfficient implementation of LMS adaptive filter‐based FECG extraction on an FPGA
Author(s) -
Vasudeva Bhavya,
Deora Puneesh,
Pradhan Pradhan Mohan,
Dasgupta Sudeb
Publication year - 2020
Publication title -
healthcare technology letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.45
H-Index - 19
ISSN - 2053-3713
DOI - 10.1049/htl.2020.0016
Subject(s) - field programmable gate array , computer science , adaptive filter , preprocessor , floating point unit , noise reduction , least mean squares filter , filter (signal processing) , reduction (mathematics) , noise (video) , artificial intelligence , floating point , algorithm , computer hardware , mathematics , computer vision , geometry , image (mathematics)
In this Letter, the field programmable gate array (FPGA) implementation of a foetal heart rate (FHR) monitoring system is presented. The system comprises a preprocessing unit to remove various types of noise, followed by a foetal electrocardiogram (FECG) extraction unit and an FHR detection unit. To improve the precision and accuracy of the arithmetic operations, a floating‐point unit is developed. A least mean squares algorithm‐based adaptive filter (LMS‐AF) is used for FECG extraction. Two different architectures, namely series and parallel, are proposed for the LMS‐AF, with the series architecture targeting lower utilisation of hardware resources, and the parallel architecture enabling less convergence time and lower power consumption. The results show that it effectively detects the R peaks in the extracted FECG with a sensitivity of 95.74–100% and a specificity of 100%. The parallel architecture shows up to an 85.88% reduction in the convergence time for non‐invasive FECG databases while the series architecture shows a 27.41% reduction in the number of flip flops used when compared with the existing FPGA implementations of various FECG extraction methods. It also shows an increase of 2–7.51% in accuracy when compared to previous works.