Fixed‐latency architecture for multi‐stage algebraic interleavers in interleave division multiple access systems

In this letter, a fixed‐latency interleaver architecture is proposed for interleave division multiple access (IDMA) systems. The existing multi‐stage algebraic interleaver suffers from the high latency originated from a series of multipliers and adders residing in each stage. In contrast, the proposed interleaver employs a simple conversion logic built by precomputing all the requisites in advance. Since the logic is completely irrelevant to the number of stages, the interleaving pattern of the proposed structure can be randomized as much as it is needed without exacerbating the latency at all.