Open AccessLow power design of explicit‐pulsed dual‐edge‐triggered level‐converting flip‐flop based on carbon nanotubes field‐effect transistors
Author(s) -
Dai Yanyun,
Yang Yanfei,
Jiang Lurong,
Tong Jijun,
Gao Faqin
Publication year - 2022
Publication title -
electronics letters
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.375
H-Index - 146
eISSN - 1350-911X
pISSN - 0013-5194
DOI - 10.1049/ell2.12620
Subject(s) - flip flop , transistor , carbon nanotube field effect transistor , electronic circuit , materials science , field effect transistor , voltage , electronic engineering , power (physics) , enhanced data rates for gsm evolution , electrical engineering , optoelectronics , engineering , cmos , physics , telecommunications , quantum mechanics
Power consumption and performance are the two main concerns in designing pulse‐triggered level‐converting flip‐flops (LCFF). In this letter, through the research on the level conversion circuits, an explicit‐pulsed dual‐edge triggered LCFF based on the carbon nanotubes field‐effect transistors (CNTFETs) is proposed by using the multi‐source voltage technology. The proposed flip‐flop increases the speed by reducing the number of transistors in the charge/discharge path. The characteristics of the CNTFETs are used to obtain transistors with different threshold voltages by changing the chiral vector to optimize the circuit structure and further reduce the power consumption. In addition, the power consumption is further reduced due to the small on‐current of the CNTFETs. The proposed novel structure is simulated in HSPICE using the Stanford model. Simulation results indicate that our proposed flip‐flop reduces 62.9% to 72.4% of power consumption and 73.6% to 89.1% of delay in comparison with other flip‐flops proposed in the references at 50% data switching activity.